Reducing leakage power in wearable medical devices using memory nap controller

The increasing demand for wearable medical devices, coupled with their short battery life, has led to a renewed interest in low power processors. A significant proportion of the total power consumed by these medical device processors, occur in the memory systems, and therefore the focus of sour work. In this paper, we propose a technique that reduces the static power consumption in caches with no side effect on processor perforemance. Our proposed architecture achieves this power saving by deterministically lowering the power state of cache lines that are guaranteed not to be accessed in immediate future cycles. We simulated our architecture across different cache configurations, using widely known CAD tools, and observed up to 92% reduction in static power consumption on SPEC2006 benchmarks with no performance penalties and minimal hardware overhead.