Influence of Passivation Oxide Thickness and Device Layout on the Current Gain of SiC BJTs

The effect of passivation oxide thickness and layout on the current gain of SiC bipolar junction transistors is reported. Different thicknesses of plasma enhanced chemical vapor deposited (PECVD) silicon dioxide in the range 50-150 nm were deposited prior to the same annealing process in N
₂
O, and their effect on the transistor gain was investigated for different device layouts. For a fixed device layout, ~60 % higher gains were observed for oxide thicknesses ranging between 100 and 150 nm with current gains of ~200 at room temperature and >100 at 300 °C. For each tested thickness of deposited oxide, device layout providing lower collector resistance achieved slightly higher gains.