eWLB SiP with Sn finished passives

The use of embedded Wafer Level Ball grid array(eWLB)[1] technology for the construction of single and multiple side by side die packages has become widespread since the introduction by Infineon technologies more than five years ago. The flexibility of this packaging to include different die material types such as Si and GaAs combined with excellent mechanical, electrical and thermal performance and the advantages of wafer level processing has been employed in a wide range of applications. More recently this flexibility has been extended to included system in package(SiP) applications with a range of embedded passive devices being combined with one or more active dies in a single package. Ideally, for motives of availability and cost, the passive devices utilized in these applications should be standard SMT devices without special requirements in terms of terminal finish. In this paper we will describe the development process involved in enabling the use of standard leadfree tin finished passive devices in embedded eWLB based SiP packages. Development of a variety of potential diffusion barriers based upon both multilayer physical vapor deposition(PVD) and electroplated metallization is explained. Significant insight into the reliability performance of the resulting packages under standard stress conditions is gained for a SiP test vehicle. The first assessment was performed using short build parts to enable a rapid feedback for the experiments. The output for this comparison was Jedec standard High Temperature Storage(HTS175°C 200hrs) stress condition. Scanning electron micrography and microsection analysis of the intermetallic region formed before and after stress with a range of barrier solutions are shown. The solution selection process is described both in terms of reliability and ease of implementation. Further development based on the initial findings suggests a path forward for potential implementation of tinned terminal passives in eWLB.