High order Dynamic Element Matching for multi-bit Delta Sigma A/D & D/A converters

This paper presents a reduced area high order Dynamic Element Matching (DEM) scheme for use with multi-bit Delta Sigma data converters. The design leverages the increased digital signal processing afforded by low geometry CMOS processes to both improve performance and reduce analog circuit area. Within the converter, dual vector feedback DEMs are combined using a noise shaped splitter, this reduces logic area while providing 2nd order mismatch error shaping.