Pure Ge mid-gap gate within an industrial high performance and low standby current 0.18 /spl mu/m CMOS process

For the first time, we demonstrate the feasibility of a Ge gate within an industrial 0.18 /spl mu/m CMOS process. The associated threshold voltage shift (/spl delta/V/sub th/) leads to an off-current (I/sub off/) reduction of as many as 6 decades. It is studied as a function of the Drain/Source anneal. No transconductance degradation is observed, which would not be the case if this shift was obtained by an increase in channel doping. In addition, we show that the SCE is well controlled and that Ge reduces the gate depletion.