Comparative Analysis of MTJ/CMOS Hybrid Cells Based on TAS and In-Plane STT Magnetic Tunnel Junctions

In the last few years, spintronics has attracted the full attention of the scientific community for the synergy it provides to conventional complimentary metal–oxide–semiconductor (CMOS) devices (nonvolatility, infinite endurance, radiation immunity, increased density, and so on). Many hybrid (magnetic/CMOS) cells have been proposed which can store and process data in both electrical and magnetic ways. Such cells are mainly based on magnetic tunnel junctions (MTJs) and are suitable for use in magnetic random access memories (MRAMs) and reprogrammable computing (magnetic FPGAs, nonvolatile registers, processor cache memories, and so on). In this paper, we report the results of exhaustive energy-performance analysis of the set of hybrid cells recently published in the literature. We explore their limits in metrics of the required silicon area, robustness, read/write speed, and consumed energy. Two different mechanisms for writing non-volatile data stored in MTJs are applied to each hybrid cell: thermally assisted switching (TAS) and spin-transfer torque (STT). All the results were obtained through simulations in Cadence Spectre 7.2. For the CMOS part, we used 45 nm predictive transistor models whereas the MTJ part was simulated using the 120 nm
$\times 120$
nm TAS Spintec model and the 100 nm
$\times 50$
nm STT Spinlib model. The results presented here are a valuable resource for future designers of hybrid devices if they need to select an appropriate hybrid cell for a target application.