Fault-Tolerant Routing Algorithm Simulation and Hardware Verification of NoC

Various software and hardware faults can destroy data transmission on the network, so it is essential to study fault-tolerant methods of Network-on-Chip (NoC). In this paper, a modified fault-tolerant routing algorithm is proposed based on the XY algorithm, which can achieve an efficient route way by resetting the route rule when error occurred on the path of chain or between the nodes. This performance shows that the fault tolerant bypassed the fault path of chain or the error nodes. A hardware design of the modified fault-tolerant routing algorithm is also introduced, aimed at the elaborating of hardware structure principle and simulating of fault tolerant routing algorithm of NoC based on FPGA. The proposed algorithm was simulated and verified on the platform of ISE Design Suite 13.3. The simulation results showed that the proposed modified algorithm is feasible. Because of the algorithm, the overall performance has improved obviously without using virtual channel, especially for the area and power consumption. At last, the proposed algorithm was verified on the FPGA platform of Nexys2 multiple sets of validate data proved that the proposed modified algorithm was reliable and feasible, and the quality of this NoC performed very well.