The effects of integrated controller techniques on the flash memories

This paper describes flash controller techniques: (1) split cache memory management which addresses architectural level issues of flash memories; (2) wear levelling and garbage collection which spreads wear-out; (3) density alteration which mitigates the effects of flash cell aging; and (4) Reed-Solomon error correction. All techniques, except RS code, are modelled and simulated in Matlab. The RS code is implemented in 65nm CMOS technology. The proposed controller increased the flash memory lifetime by 128X with a 4.1X increase in latency.