An error-compensation A/D conversion technique

An architecture for a successive-approximation analog-to-digital (A/D) converter using switched-capacitor techniques is described. The converter design consists of a comparator, two operational amplifiers, and several unit capacitors. The simplicity of the circuit is comparable to that of cyclic A/D converters. An error-compensation technique for reference generation is also proposed that improves the resolution of the converter with relatively few operations. Based on the principle of charge redistribution, the capacitor mismatch error is first stored in an analog manner and the necessary voltage references are generated accurately. The error is then compensated in subsequent conversions. Since this is done in a parallel manner, the speed of the converter is not compromised. The converter has been realized using a 1- mu m CMOS technology. The test results indicate that with a conversion time of 20 mu s, the chip performs as a monotonic 11-b converter with +or-0.9 least significant bit (LSB) differential and +or-1.4 LSB integral nonlinearity.<
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