Low dead time digital SPAD readout architecture for realtime small animal PET

CMOS integrated SPAD array design normally enforces a compromise between circuit functionalities and optical detection fill factor, never quite reaching the ideal detector configuration when both are integrated together on the same substrate. The emergence of vertical 3D integrated circuits (3DIC) changes this restriction and further adds in heterogeneous electronic integration, opening technological combinations otherwise difficult or impractical to obtain. Using this approach, a heterogeneous SPAD array detector prototype with digital readout for small animal PET was developed. It is based on Global Foundries 130 nm CMOS for digital and quenching circuits and on Teledyne Dalsa 0.8 μm HV CMOS process for the SPAD arrays. This paper focuses on the realtime digital architecture tailored for small animal PET scintillation detection, where in addition to tight timing and energy resolution, low PET dead time and high spatial resolution are required. A discriminator circuit is proposed to retain first-photon timing information while protecting against dark count rate triggering. The system provides two operational modes: a slower oscilloscope-like mode and a high rate PET mode providing 2.2M singles per second on a single 200 MHz LVDS transmitter. Performances in terms of electronic jitter and event detection are reported based on simulations.