Current source based standard-cell model for accurate timing analysis of combinational logic cells

Timing verification is an essential process in nanometer design. Therefore, static timing analysis (STA) is currently the main aspect of performance verification. Traditional STA is based on lookup tables with input slew and output load capacitance. It is becoming insufficient to accurately characterize many significant aspects of the conventional cell delays models, such as: the process variations, nonlinear waveforms, nonlinear loads, and multiple inputs switching (MIS). Therefore, the current trend in modern designs is to use current source based models (CSM), which model MOSFETs as a transconductance. This paper proposes a CSM for combinational logic cells which can accommodate single input switching (SIS) signals. It can also handle where small capacitances are connected at the gate output, while fast ramp signals are applied to the gate input. When compared with ELDO, the proposed model produces more accurate stage delay than that obtained from the standard cell lookup tables.