Stud bump process for flip-chip research: Improve UPH of stud bump

A-03 Flip-Chip in Chip card is a kind of new technology applied widely in the semiconductor field. It is becoming a big challenge for the stud bump on the wafer due to smaller and smaller bond pad, consequently smaller bump size with more stable process control becomes very critical due to UPH (Units Per Hour) dropped greatly. In this paper, the process of stud bump is briefly introduced and key requirements are defined. The common mechanism of different stud bump modes is clarified with process procedure. By comparison of different stud bump modes, these main issues in manufacturing line can be addressed by 6 sigma methodology. Then the key factors are filtered by DoE experiments. After that, data validation is performed based on the results of Box plot of CEAD software. The optimized process parameters are drilled for mass production to achieve higher and stable UPH. The whole evaluation can be finalized by data analysis.