Hardware accelerator implementation on FPGA for video processing

Intelligent video surveillance for security purposes requires real-time performance. Such performance requires large amount of resources, including bandwidth, processing power and memory. In addition, the deployment of such system requires an embedded solution with low cost and power. However, embedded systems have limited resource for processing. The advancement of Field Programmable Gate Array (FPGA) enables development and implementation of a system with reconfiguration capability. Besides, it also offers competitive cost in comparison to an Application Specific Integrated Circuit (ASIC) deployment of the system. In recent years there is an increase research in the effort to implement video surveillance and processing system using FPGA. The computational heavy processing of streaming frames in video processing is implemented using hardware accelerator, a dedicated processing unit for the video processing algorithm. Majority of the research on video processing hardware accelerator are to develop a dedicated hardware implementation of the video processing algorithm. This research aims to investigate and propose a general model from hardware accelerator development which has the capability to accommodate different video processing applications.