Integration of III-V nanowires on Si: From high-performance vertical FET to steep-slope switch

In this paper, we present recent progress in the integration of vertical III-V nanowire-channels on Si by selective-area epitaxy and demonstrations of high-performance III-V vertical surrounding-gate transistors with high-k dielectrics with an EOT of less than 1 nm, modulation doping technique, and challenges in steep subthreshold-slope switching using III-V nanowire/Si heterojunctions as building blocks for low power circuits.