Leading one detectors and leading one position detectors - An evolutionary design methodology

Design of leading-one detector (LOD) and leading-one position detector (LOPD) are important as they are used for the normalization process in floating-point multiplication, floating-point addition/subtraction and in logarithmic converters. In this paper, the authors propose various gate-level architectures for LOD and LOPD. The LOD and LOPD circuits are evolved using the evolutionary algorithm (EA) and using the evolved lower-order gate structures, various higher-order circuits are constructed. To obtain better results, the EA is modified and a novel shuffling operation is performed to prevent the algorithm from settling in the local minima. Then the constructed LOD and LOPD circuit is synthesized using Cadence® RTLCompiler® using TSMC 180nm library. The LOD and LOPD circuits can be implemented in an Application Specific Integrated circuit (ASIC) or in a Field Programmable Gate Array (FPGA), and hence it is independent of the technology library. Perhaps the evolution can also be made as an intrinsic process during the application run time and the evolved best gate structure can be chosen. We restrict this paper to the extrinsic evolution of LOD and LOPD gate level architectures.