Design and implementation of a Chaotic Cipher block chaining mode for image encryption

This paper proposes and investigates a Chaotic Cipher Block Chaining mode (CCBC) which is to improve the security of a cryptographic algorithm and more resisting cryptanalysis. The size of both block and key are 512-bits. This approach makes the size of key greater than those of the current Data Encryption Standard (DES) and Advanced Encryption Standard (AES). The security analysis process proves that the proposed algorithm can resist the statistical and differential attacks. It also passed the key sensitivity test. The experimental results on Field Programmable Gate Array (FPGA) show the feasibility and effectiveness of the cryptosystem and indicates the trade-off between secure/performance/efficient and architecture hardware design.