New Beta-Matrix topology in CMOS32nm and beyond for ESD/LU improvement

This paper is focused on the optimization of Beta-Matrix power device to protect thin oxide GO1 =1 V and thick oxide G02=1.8V. The study investigates Beta-Matrix topology and particularly the impact of elementary pattern on device behavior. This work is mainly carried on 3D TCAD simulations. The best configurations, with lower voltage triggering have been realized in CMOS32nm high k metal gate and characterized thanks Transmission Line Pulse (TLP) with 100ns width.