The impact of lot-to-lot and wafer-to-wafer variations on SPC

In this paper we point out that the application of standard SPC charts for process control during wafer fabrication could lead to errors due to the presence of the lot-to-lot and wafer-to-wafer variations. We illustrate that the error could increase the "lots-at-risk" by as much as 17%. We present a new SPC model which accounts for the lot-to-lot and wafer-to-wafer variations. Then, we present an adaptive sequential two-lot control policy, where we sample the successive lot when there is an out-of-control signal, and investigate for the process shift only when the successive lot also gives an out-of-control signal. This adaptive method outperforms the static policy as long as the lot-to-lot variance is smaller than the wafer-to-wafer variance. However, when the wafer-to-wafer variance is higher than the lot-to-lot variance, the information from a successive lot is less variance than the information from additional wafers in the same lot.