Impact of fin width scaling on carrier transport in III-V FinFETs

Power constrained scaling mandates that devices for future nodes beyond 14nm will need to maintain high drive currents at low supply voltages. In this regard, III-V FinFETs have attracted much interest due to their superior transport properties [1-2]. However in order to maintain electrostatic integrity, multi-gate architectures such as the FinFET will be implemented simultaneously. As shown in figure 1, patterning of III-V substrates into narrow Fin structures can have an adverse impact on channel mobility due to additional scattering mechanisms coming from side wall roughness. Further the potentially high interface state density at the III-V sidewall - High-k interface could lead to further degradation in channel mobility. In this work we quantify the mobility degradation through hall measurements on long channel FinFETs realized on In
_0.7
Ga
_0.3
As quantum well substrates. Further, we extract the percentage degradation arising from side wall roughness and project the expected mobility down to 10nm Fin widths.