Reliability of CMOS on Silicon-on-Insulator for Use at 250 $^{\circ}\hbox{C}$

This paper deals with the reliability of a 1.0- μm CMOS-silicon-on-insulator (SOI) process, which is intended for use at 250
^°
C. The goal is to give an overview of the most important reliability aspects that concern devices and circuits at temperatures of 250
^°
C and above. The investigated reliability aspects are the gate oxide integrity in terms of time-dependent dielectric breakdown measurements, electro- and stress migration, and the EEPROM reliability such as the data retention and the endurance, as well as transistor aspects (e.g., hot carrier, negative bias temperature instability) and the long-term stability of a ring oscillator and a band-gap reference. As most of the commonly applied methods for accelerated reliability testing and analysis are not designed to be used at such high temperatures, this paper evaluates in which way the known models can be applied and which physical mechanisms have to be considered. Since temperatures of 250
^°
C and more are necessary for testing, the investigations also yield an estimate of the temperature limit of use for CMOS on SOI. The results indicate that the use of CMOS on SOI is, in principle, possible up to 400
^°
C.