Analysis of thin gate oxide degradation during fabrication of advanced CMOS ULSI circuits

The electrical characteristics uniquely associated with the thin gate oxide degradation of the advanced CMOS technology in manufacturing were determined for the first time. They were different from Fowler-Nordheim (F-N) stress, and therefore, cannot be simulated by the F-N stress. The p/sup +/ thin gate oxides were found to be inherently more susceptible to gate oxide degradation than the n/sup +/ gate oxides. The p/sup +/ oxide degradation is caused by a combination of the process-induced defect and plasma charging. The nature of the defect and its formation were identified by electrical and physical analysis. The defect formation was modeled. The p-channel gate oxide degradation will be worse with gate oxide scaling, and may limit the device scaling.