A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit

This paper presents circuit techniques to reduce both active and standby mode power, especially at room temperature (RT). A bit-line power calculator is used to adaptively set the cell supply voltage (VCS) in the active mode. A digitally controllable retention circuit regulates VCS in the standby mode with small control power. These circuits are implemented in a dual-power-supply SRAM in 28-nm CMOS technology. Compared with the conventional scheme, the power consumption in the active and standby mode at 25
^°
C is reduced by 27% and 85%, respectively.