Cost-Effective Hardware-Sharing Design of Fast Algorithm Based Multiple Forward and Inverse Transforms for H.264/AVC, MPEG-1/2/4, AVS, and VC-1 Video Encoding and Decoding Applications

In this letter, multiple forward and inverse fast algorithm based transforms and their hardware-sharing design for 2 × 2, 4 × 4, and 8 × 8 transforms in H.264/AVC, and the 8 × 8 transform in audio video coding standard, 4 × 4 and 8 × 8 transforms in VC-1, and DCT/IDCT in MPEG-1/2/4 are developed with a low hardware cost for multistandard video coding applications. Compared with the directly combined fast transforms without shares, the proposed low-cost 1-D architecture reduces shifters by 67%, adders by 73%, and gate counts by 53.4%. The hardware-sharing efficiencies of shifters and adders in the proposed 1-D transform design are 32% and 25% more than those in the previous design, respectively. By 0.18-μm CMOS technology, the proposed 2-D transform architecture has less normalized power per mode and larger normalized hardware efficiency than the previous multiple-standard designs. The cost-effective 2-D full pipelined transform achieves multistandard real-time 1080HD at 60-Hz video encoding and decoding applications.