Clock period optimization in a multiphase edge-clocked circuit constrained to a maximum number of phases

Presents a timing graph technique for the optimization of multiple-phase edge-clocked circuits. By using this method, the timing of these synchronous systems can be analyzed and designed accurately, taking into account the corresponding temporal parameters involved. An optimization algorithm, which includes the effects of the setup and hold time and the propagation delays of the registers, is introduced. The optimal phase distribution is obtained by means of an integer linear program. An iterative procedure for constraining the maximum number of phases is also proposed.