Device considerations of planar NAND flash memory for extending towards sub-20nm regime

Device considerations of planar NAND flash memory for extending towards sub-20nm regime have been reviewed. A transient deep-depletion phenomenon of p-type floating gate, which affects the program efficiency of a scaled device, is described. The endurance of the p-type floating gate has been improved with an aid of hole compensation on the charge trapping. Meanwhile, solutions are required to overcome the lowering of the boosting potential by the BTBT generation with increased lateral electric field between the channels as well as the BTBT generation with increased vertical electric field. Furthermore, the conventional DIBL effect also significantly affects V
_T
shift on the scaled-NAND string. Regarding the reliability, the electric field crowding on the top of the floating gate should be relieved and it has been revealed that the endurance behavior has been changed by the increase of edge tunneling current during the erase operation.