A 70MS/s 69.3dB SNDR 38.2fJ/conversion-step time-based pipelined ADC

A Nyquist ADC with time-based pipelined architecture is proposed. The proposed hybrid pipeline stage, incorporating time-domain amplification based on a charge pump, enables power efficient analog to digital conversion. The proposed ADC also adopts a minimalist switched amplifier with 24dB open-loop dc gain in the first stage MDAC that is based on a new V-T operation, instead of a conventional high gain amplifier. The measured results of the prototype ADC implemented in a 0.13μm CMOS demonstrate peak SNDR of 69.3dB at 6.38mW power, with a near rail-to-rail 1MHz input of 2.4V
_P-P
at 70MHz sampling frequency and 1.3V supply. This results in 38.2fJ/conversion-step FOM.