Signal integrity issues due to ESD events in high-speed CMOS comparator

This paper is mainly focused on analyzing the behavior of the output data of a CMOS latched comparator subjected to the Human Body Model (HBM) Electrostatic Discharge (ESD) test event. The importance of the comparator circuit in the applications of data transmission is illustrated. Several tests using the Cadence IC 5.3 software were carried out in order to investigate the accuracy of the output data signal. The tests were computed for the high and low level of the clock. The malfunction of the comparator structure due to the effects of the electrostatic field is investigated. The functioning of the circuit was improved by adding decoupling capacitors with protective properties.