An energy-efficient BBPLL-based force-balanced Wheatstone bridge sensor-to-digital interface in 130nm CMOS

An energy-efficient time-based sensor interface in 130nm CMOS technology is presented for resistive sensors. Traditionally resistive sensors are interfaced with a voltage divider or a Wheatstone bridge to transform the sensor signal to a voltage. However, both the voltage divider and the unbalanced Wheatstone bridge are highly affected by supply voltage variations, especially in smaller CMOS technologies with low supply voltages. As alternative to ratiometric measuring, this paper presents a force-balanced Wheatstone bridge interface circuit with a highly digital architecture, that offers the advantage of low power consumption with highly improved overall PSRR. It has a noise-frequency-independent PSRR of 52dB for in-band supply noise and supply noise amplitudes up to +10dB
_FS
, which is an improvement of 46dB over the voltage divider and of 26dB over the unbalanced Wheatstone bridge. Apart from the sensor calibration, no other calibration or absolute precise clock or voltage references are needed due to the BBPLL-based architecture. The complete interface consumes only 124.5μW from a 1V supply with 10kHz input bandwidth and 10.4 bit resolution and 8.9 bit linearity, resulting in a state-of-the-art sensor Figure of Merit of 13.03 pJ/conversion.