Thermal characterization of chip packages-evolutionary development of compact models

The expanded R/sub jc/ methodology, first proposed in 1989, makes it possible to extend the use of this common figure-of-merit to chip packages with nonisothermal cases. This proposal spurred considerable debate and contributed to renewed efforts to provide "compact" thermal models of single chip packages, for preliminary design, as well as for detailed numerical simulation of populated printed circuit boards. This presentation offers a review of the development of this modified R/sub jc/ methodology and its efficacy in replicating the chip, or junction, temperature predicted by detailed numerical simulation.