A simplified mathematical model for DC-balancing and capacitor ripple reduction in 3-level inverters

Because of its cost implications, DC balancing and third harmonic ripple on the capacitor voltages is a point of concern in 3-level inverters. Hence, a reasonable amount of research has been reported, in connection to this issue. In most of the publications, the problem is dealt in a way which is specific to the particular application or to the PWM technique used. A general mathematical model has not been reported yet. This paper presents an in-depth mathematical analysis and a solution which follows a model-based approach. It also presents a general model of the closed-loop system, both for voltage balancing and ripple reduction. Experimental results are presented, which prove the validity of the model.

I. Introduction

It is well known that, in most applications, a decent amount of efficiency can be gained by replacing a 2-level inverter with a 3-level inverter [6]. Also, by migrating to a 3-level inverter, it is possible to reduce the ripple in the output current or to reduce the filter inductance size [8]. This is the reason that the use of this topology is expected to increase in the fields such as grid connected PV, UPS systems etc.