Implementation of a bandwidth optimized wideband-integrator on FPGA

Analysis of digital design and implementation of Nam Quoc Ngo's 32 bit integrator is being presented in this paper. The design objective is to realize a wider bandwidth integrator. Proposed design is optimized using conditional sum adder for addition, Radix 4 Booth with Wallace tree carry save adder algorithm for multiplication and a modified algorithm to calculate 2s complement of a binary number. The time complexity of proposed design is compared with hardware design generated by Matlab Xilinx system generator and design by default hardware of DSP48 slices on virtex-5. Proposed design is having larger bandwidth compared to the design by system generator and DSP48 slice based design.