Modeling and design of a dual-residue pipelined ADC in 130nm CMOS

A 9-bit 50MS/s dual-residue pipelined ADC is modeled and analyzed. The first stage is a modified pipelined ADC stage, while the other stages use an interpolator to resolve the signal; the focus is on designing these stages. A new successive approximation based interpolator (SAI) is proposed. This interpolator is insensitive to parasitic capacitances, and makes it possible to utilize open loop residue amplifiers. The dual-residue architecture is insensitive to the gain of the residue amplifiers, and only a matching between two amplifiers is necessary. Limiting parameters of the ADC are the offset in the residue amplifiers, as well as gain mismatch between the amplifiers. The ADC with the SAI got an ENOB of 8.99-bit when simulated without offset and gain mismatch. The maximum allowed offset voltage of the residue amplifier is equation, and with this offset voltage for all the amplifiers in the ADC the ENOB dropped to 8.61-bit. The maximum allowable mismatch between the two residue amplifiers is equation, with this mismatch the ENOB is 8.85-bit. Both these demands should be possible to reach without the use of calibration. With a zero-crossing based amplifier the last 8 stages of the ADC has an estimated power consumption of 2.1mW.