Experimental exploration of ultra-low power CMOS design space using SOIAS dynamic V/sub T/ control technology

Supply voltage scaling to 1V and below, with associated V/sub T/ scaling, has been identified as a key approach for energy efficient high performance computing. However, V/sub T/ scaling is ultimately limited by increasing subthreshold leakage current. We experimentally explore the low V/sub DD/, V/sub T/ design space using a variable threshold voltage CMOS technology, Silicon-On-Insulator-with-Active-Substrate (SOIAS), which we have developed. Energy consumption modeling indicates that the dynamic V/sub T/ control afforded by SOIAS can lead to significant energy savings without sacrificing performance for systems that operate in burst mode, for example when limited by user input rate. This is of particular importance in battery operated systems.