Performance of a full-hardware PTP implementation for an IEC 62439-3 redundant IEC 61850 substation automation network

Seamless redundancy and precise clock synchronization are integrated fully in hardware (FPGA) with no processor support. The interaction between redundancy and clock synchronization is explained. Redundant synchronization messages are not be discarded, but used to improve clock accuracy. Measurement results confirm the validity of the concept. Performance of the full-hardware implementation is compared with that of a conventional software-hardware implementation.