Hardware-software aspects of shift-register based NEWS networks for the focal plane

Processing medium-size images in the chip where they are sensed has now become technologically possible. Such devices are called artificial retinas. In order to set up a whole programmable boolean array processor in the focal plane, a specific NEWS interconnection network is required that trades off between speed, silicon area, energy consumption, and controllability. Shift-register based solutions are considered here. A scalable design is presented in which silicon area only is minimized, as the major constraint. Its performances are then quantitatively analysed with respect to the three other criteria and shown to present some significant weaknesses. This leads to relax the area constraint and to propose a second solution that improves the overall trade-off at the expense of a small area increase.