On the analysis of routing, cells and adjacency faults in CMOS digital circuits

The continuous increase in integrated circuits (IC) complexity is pushing test preparation into higher levels of representation. High level techniques do not take into account the physical design; even logic level test preparation ignores it. As a consequence, estimations of test quality, and IC quality in the IC design environment are missing, or very inaccurate. Therefore, there is a need to capture low level (i.e., defects level) test information, for further use at higher levels. In this paper, two aspects have to be considered: (1) the efficient extraction of faults from the layout; and (2) the mapping of such faults into higher levels of representation. Bridging defects are selected, as they are associated with the most likely faults in today's process lines. The relative importance of routing, cells and adjacency faults is investigated, for digital CMOS standard cells layouts, generated with different libraries. It is shown that realistic routing faults can be used to achieve a good estimation of the defect level. However, depending on the layout of the cells, the cell and adjacency faults may play an important role in the defect level estimation. Results for commercial and proprietary cell libraries are presented, pointing out its influence on the overall quality of the IC's.