Ultra High Speed Digital Down Converter Design for Virtex-6 FPGAs

This paper describes the design and optimization of an ultra- high speed Digital Down Converter (DDC) for a realization by FPGAs. After explaining the general structure of the Digital Down converter we describe in detail how to implement such a design in order to process a digital, massively parallelized signal. The necessary optimizations to achieve an efficient implementation in state of the art FPGAs are explained and a case study for an FPGA optimized Digital Down Converter design suitable for OFDMA systems is presented. The key components of this DDC are highly parallelized half-band filters which are optimized for Virtex-6 FPGAs and enable the design to decimate a 6 bit wide input signal with a sample rate of 25 GS/s into a 16 bit 1.5625 GS/s signal while achieving an attenuation of around 35 dB. The results include the resource consumption of the DDC for a Virtex-6 XC6VHX380T FPGA as well as the filter response to a chirp test signal.