An evaluation of the application dependent FPGA test method

In this paper we evaluate the application dependent FPGA (Field Programmable Gate Array) test method which uses an ASIC BIST (Application Specific Integrated Circuit Built-in Self-Test) techniques and tools and efficiently utilizes the properties of nowadays FPGA devices, such as the partial runtime reconfiguration. The method splits the tested circuit and then uses partial reconfiguration to change the role of the partitioned modules, which may act as testers or as response analyzers. Circuit partitions are translated to an ATPG (Automatic Test Pattern Generator) readable format and the deterministic test vectors are generated. The compression tool is used to compress test patterns, thus it is not required to create additional test access interfaces or to use multiple reconfigurations. We show that the usage of the method reduces test time and memory requirements and it leads to good test coverage results. Each step of the design flow is described and evaluated in detail as well as the experimental results and the hardware.