BiCMOS circuits for DPCM coders in HDTV systems

Three different strategies used to enhance the speed performance of differential pulse-code-modulation (DPCM) coders are reviewed. The first strategy is the reduction of the number of components located in the time-critical recursive loop. The second is the use of a BiCMOS technology, and the third is the development of high-speed circuit techniques. Prototype chips prove that a 2.5- mu m process is feasible for implementation of DPCM coders operating at 54 MHz. Another test structure shows a BiCMOS sequencer with 64 product terms running at 80 MHz with 125-mW power consumption.<
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