Design and implementation of low power clock distribution network

Clock distribution network forms an integral part of any digital circuit. It consumes a large part of the total circuit power, which is not desirable. Different techniques are employed up till now to reduce the clock power. In this paper we have demonstrated how clock power can be reduced significantly by distributing it at reduced supply voltage. The clock distribution network is designed and simulated in 0.25µm technology. It is simulated at different frequencies of 10MHz, 100MHz, 200MHz, 250 MHz and 400MHz achieving power reduction of about 53%, 44%, 41%, 24% and 5% respectively.