Very high throughput FPGA design for vertical rotational transform of HEVC emergent video coding standard

This paper presents a dedicated architecture for the Rotational Transform (ROT), which is one of the novel tools proposed by the HEVC emergent video coding standard. The main goal of this coding tool is to achieve higher energy compaction of the main transform coefficient matrix and thus improve entropy encoding and minimize quantization error. The architecture was designed with nine pipeline stages, targeting very high processing rates. The designed architecture was described in VHDL and synthesized for an Altera Stratix III FPGA. The results show that the architecture achieves a maximum operation frequency of 197.98 MHz. Processing eight samples per clock cycle, this architecture reaches a processing rate of 1.58 billion samples per second, allowing it to process videos up to UHDTV in real time (30 frames per second).