Advanced low power interconnect signaling schemes

In this paper a number of low-swing on-chip interconnect schemes will be reviewed and their effectiveness and limitations will be analysed, especially on power dissipation, delay and area. This paper describes the design of interconnect scheme (mj- lc) and (mj-c) for driving signals on the global interconnect lines. The proposed signaling schemes is implemented on 1.0 V 0.13 μ m CMOS technology, for signal transmission along a wire-length of 10 mm and the extra fan-out load of 2.5 pF (on the wire)as in previous work for a standard benchmark. Comparative evaluation of the proposed schemes is carried out with two other related designs in terms of power consumption, area, delay. The simulation results show a significant reduction of energy-delay product by up to 47% and 38% and energy-delay product by up to 34% and 49%, when compared with other counterpart low- signaling schemes.