Abstract:
In scaled VLSIs, a reliable robust circuit system is essential for the sustainable secure society. The threat to the VLSI system is caused by device, circuit or system is...Show MoreMetadata
Abstract:
In scaled VLSIs, a reliable robust circuit system is essential for the sustainable secure society. The threat to the VLSI system is caused by device, circuit or system issues. This forum provides an overview of the technical challenges as well as recent advances in circuit and system-level reliable VLSI technologies. The forum starts with the overview on the robustness and fault tolerance requirements for microcontrollers in automotive applications. The e-mobility and the new safety norm ISO 26262 affect future requirements on semiconductors. The second talk reviews recent trend of CMOS variability, followed by measured examples on static variations (process) as well as temporal variations (RTN, NBTI). Methods for variability characterization, minimization, and mitigation is also covered. The forum also has three presentations about reliable memory circuits. To enable high-density and low-power SRAMs with robust reliability and fault-tolerance, a variety of energy-efficient, variation-tolerant, and adaptive circuits are reviewed. Embedded non-volatile memory (eNVM) has greatly contributed to the recent growth of MCU market. The current eNVM technologies for highly reliable applications and future directions such as STT-MRAM and ReRAM are presented. The increase of SSD storage capacity drastically increases the total amount of circuits in memory chips inside SSDs. High relaiable SSD controller technologies such as the block device (sector unit Read/Write device) management and the error correcting code are presented. Then, the robust system design is presented. New approaches to thorough test and validation that scale with tremendous growth in complexity and cost-effective tolerance and prediction of failures in hardware during system operation are discussed. The sevnth talk overviews the reliability measures and CMOS failure mechanisms for analog circuits. Simulation techniques to predict performance degradation or device failure is also presented. This forum also h...
Published in: 2012 IEEE International Solid-State Circuits Conference
Date of Conference: 19-23 February 2012
Date Added to IEEE Xplore: 03 April 2012
ISBN Information: