The implementation of modulator using FPGA technology for W-CDMA WLL

This paper describes the design and implementation of the modulator in subscriber unit for wideband code division multiple access (CDMA) wireless local loop (WLL) testbed with 5 MHz bandwidth using Field Programmable Gate Array (FPGA) technology. The modulator presented in this paper provides two main functions: it carries out the complete digital modulation process for the reverse link and deinterleaves the forward-link symbols received from the symbol combiner of the demodulating unit. Also, the spectral degradation due to quantization error of filter coefficients and truncation of filter output is simulated. Filter output signals obtained from this implemented modulator are also included.