Neural CMOS-Integrated Circuit and Its Application to Data Classification

Implementation and new applications of a tunable complementary metal–oxide–semiconductor-integrated circuit (CMOS-IC) of a recently proposed classifier core-cell (CC) are presented and tested with two different datasets. With two algorithms—one based on Fisher's linear discriminant analysis and the other based on perceptron learning, used to obtain CCs' tunable parameters—the Haberman and Iris datasets are classified. The parameters so obtained are used for hard-classification of datasets with a neural network structured circuit. Classification performance and coefficient calculation times for both algorithms are given. The CC has 6-ns response time and 1.8-mW power consumption. The fabrication parameters used for the IC are taken from CMOS AMS 0.35-
$\mu{\rm m}$
technology.