Asynchronous design in dynamic CMOS

The design for dynamic CMOS cells that can be used as building blocks in an asynchronous pipeline are discussed in this paper. The proposed circuit elements are variations on TSPC logic using Sutherland's micropipeline structure combined with dual rail logic to detect operation completion. The resulting cell occupies more area than a TSPC cell, but has higher functionality because of the built-in data flow control mechanisms provided by the handshake signaling of the micropipeline structure.