A high speed signal processing machine — its architecture, language and compiler

A systolic array architecture computer (FXCQ) has been designed for signal processing. It can handle floating point data at very high speed. It is composed of 16 processing cells and a cache that areconnected linearly and form a ring structure. All processing cells are identical and programmable. Each processing cell has the peak performance of 20 million floating-point operations per second (20M FLOPS). The machine therefore has a peak performance of 320 MFLOPS. It is integrated as an attached processor into a host system through VME bus interface. Programs for FXCQ are written in a high-level language — B language, which is supported by a parallel optimizing compiler. This paper describes the architecture of FXCQ, B language and its compiler.