Impact of oxidation and reduction annealing on the electrical properties of Ge/La2O3/ZrO2 gate stacks

The current work is discussing the surface passivation of Germanium surfaces by using layered La
₂
O
₃
/ZrO
₂
high-k dielectrics deposited by Atomic Layer Deposition for use in Ge-based MOSFET devices. The improved electrical properties of these multilayered gate stacks exposed to oxidizing and reducing agencies in presence of thin Pt cap layers are investigated. The results suggest the formation of thin intermixed La
_x
Ge
_y
O
_z
interfacial layers with thicknesses controllable by oxidation time. An additional reduction treatment further improves the electrical properties of the gate dielectrics in contact to the Ge substrate. The scaling potential of the respective layered gate dielectrics used in MOS-based device structures is discussed. As a result low interface trap densities of the ALD deposited La
₂
O
₃
/ZrO
₂
layers on (100) Ge down to 3·10
¹¹
eV
^-1
cm
^-2
are demonstrated. A trade-off between improved interface trap density and equivalent oxide thickness is found.