Testability of sequential circuits with multi-cycle false paths

This paper investigates the relationship between multi-cycle false paths and the testability of sequential circuits. We show that removal of multi-cycle false paths (either by circuit restructuring or by proper state encoding) improves circuit testability, though not as significantly as one would expect. We then investigate the use of partial scan. We demonstrate the inability of current structure-based scan register selection techniques to select the minimum possible set of registers. We propose a novel and efficient way to exploit the causes of multi-cycle false paths to judiciously choose scan registers for maximum possible testability.