Sizing low-voltage, low-power CMOS analog circuits

The g
_m
/I
_D
methodology allows designing Low-Voltage Low-Power CMOS circuits without the need to iterate SPICE simulations. The methodology leads directly to optimal implementations provided clear objective can be laid down first. Generally the method proceeds according to the steps below: a) set-up look-up tables making use of Spice or BSIM (g
_m
/I
_D
's from 10 to 15 V
^-1
are considered primarily to minimize power). b) choose primary variables c) estimate gate lengths in accordance with desired gain and transit frequencies. d) evaluate parasitic capacitances. e) evaluate currents and widths taking advantage of specifications. Since closed-form solutions cannot be found generally in complex circuits, some assumptions may be required wherever necessary. f) re-iterate drain and width evaluations to get rid of the assumptions. g) check the result by running a circuit simulator like Spice.